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Recent content by mostafa272

  1. M

    I need some information about NoC area consumption

    Hi For my thesis I need some information about area consumption of a real NoC-based System-on-Chip. I want to know in a real NoC, what percent of the NoC area is for cores (is utilized by cores) and what percent is for network components( links+ routers). I need some papers about it. please...
  2. M

    flits flow control in a router of network-on-chip

    Hi I work on a NoC that it is using Hermes router in it's structure. I want to control flit flows on channels before entering to the input ports but I don't know how can I do this.It uses some signals like rx,rx_clock,credit_o to control connections. I want to stop flits flow when a packet is...
  3. M

    making some changes in NoC blocks to be faulty

    I use Atlas Framework that it makes VHDL code for NoC automatically. It uses credit-based communications for flow controling.For testing my design, I need to assume different faults for input ports blocks and links. for input ports,I give it: rx<='0'; to it doesn't recieve any packets from...
  4. M

    making some changes in NoC blocks to be faulty

    Hi I have a NoC that is implemented with VHDL. I work on fault tolerant design and I want to make some changes in code to some blocks like input ports or links be faulty, but I don't know how can I do this?I use some bits to show faulty or normal states ,but it's not enough and I should do some...
  5. M

    problem with creating layout from tpr file in tanner l-edit

    Hi I synthesized my verilog code with Leonardo Spectrum. then I converted the verilog file to tpr file.but when I try to make layout from this tpr file with CUB library(cub.tdb), Ledit makes a wrong layout that it has very many DRC errors and some connections don't reach to any signals. I...
  6. M

    there is no transistor for some input signals in SPICE netlist

    I added node name aliases as comment to extracted netlist, and I have it: * 124 = a[0] (6.4,16452.4) * 124 = b[3] (1130.5,8134.5) * 124 = cn (-65.8,-418) * 124 = m (-107.3,-418) * 124 = s[0] (1130.5,3136.5) * 124 = U13/ix5651/A (5.8,16359.4) * 124 =...
  7. M

    there is no transistor for some input signals in SPICE netlist

    Hi I extracted SPICE netlist from layout with L-edit but there is no transistor for some signals,for example s[0] is a input signal,but I don't know where is it in this netlist.I attached the netlist, please see it. Thanks
  8. M

    problem with finding input and output transistors in a spice netlist

    I work with L-Edit to create Layout and extract netlist from it. It creates name of transistors automatically when I try to extract spice netlist. the count of transistors is very many, and I can not find input and output transistors from layout or netlist.please show me a good way!
  9. M

    problem with finding input and output transistors in a spice netlist

    Hi I wrote a ALU with Verilog code,then I made tpr file from it,and in next step I created it's layout in L-Edit. Now, I like to extract it's netlist from layout,but the count of transistors is very very many and I don't know which of them are input transistors and which of them are output...
  10. M

    I want to synthesize my design without optimization in design compiler

    My design is a low power multiplier. Previous jobs were simulated with HSPICE,but implementation of a big circuit in a spice netlist is not easy for me. so I want to synthesize previous designs and my design with powerful ASIC tool like design compiler. when I try to synthesize previous jobs, it...
  11. M

    I want to synthesize my design without optimization in design compiler

    Hi I wrote verilog code for my design in gate level,but when I try to synthesize it with Synopsys Design Compiler, it changes my design automatically for optimization,but I don't like to change my design. I want to synthesize exactly what I wrote. Is there any way to force it to synthesize my...
  12. M

    problem with finding equal layers in two different tdb file

    Hi the mhp_n05.tdb is a basic Tanner database file to make different layers for layouts in Ledit.I have another library (cub.tdb) that has different layers from mhp_n05.tdb. I don't have extract file for cub.tdb,so I want to change mhp_n05.ext to know cub.tdb layers,but I don't know exactly...
  13. M

    problem with using CMOS switches in Synopsys Design Compiler

    Hi I want to synthesize my verilog code with Synopsys Design Compiler, but it makes some errors because I used the nmos and pmos switches in my design.I must use CMOS transistors in my design because it has a special structure. how can I solve this problem?
  14. M

    I need a extraction file to extract netlist from layout in Ledit

    Hi I have an old tdb file(cub.tdb) to create Layout from tpr in Tanner Ledit. I made Layout with this library but I don't have it's extraction file to extract spice netlist. If you have this file or you know a website to download it,please introduce it. Thanks
  15. M

    problem with SPICE netlist extraction from layout with L-edit

    Hi I want to extract spice netlist from layout with L-edit.the layout is made from a tpr file.but when I try to extract spice netlist, I receive following error: --------------- ERROR: Incorrect connection definition syntax on line 12 in file: MHP_N05.EXT Layer "n well wire" does not exist...
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