Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
all the delay are coming from the SHA256_CASE. I dont quite understand what you mean by cutting the combinatorial paths and inserting registers ? In the case of the Datapath.png should i remove some of the delay type and replace it with a register? To do that, i need to rewrite my code or am i...
I've been trying to implement a SHA256 design on my Arty a7-35t FPGA. When i try to implement the design, my timing fails wih the following values : WNS: -5.969, TNS : 428. It s my first time encountering this kind of problem and i am not sure how to tackle it. I will post some screenshots under...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
