Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
When you say I have to balance the whole clock tree from clk_1 root, what does you mean by that?
I have tried in Quartus to setup the Clk_g as a derived clk of Clk_1, but it doesn't seem to change anything. The strange thing is - if I say the derived clk has an offset of 0 ps compared to clk_1...
Hi,
I have tried to read about gated clocks in different posts, but haven't been able to find a good answer, so I create a new post.
I have a Clk_1 which I gate and call Clk_g. The block that runs on Clk_g read some signals from a block running on Clk_1.
My problem is I get some Hold-time...
array of std_logic_vector
How do you index 1 bit throug the array?
Using the previous example:
type memory is array (INTEGER range <>) of std_logic_vector(7 downto 0);
signal GetDescDevice : memory(0 to 92); -- a 93 byte character array
to write one byte you'll refer to :
GetDescDevice(3)...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
