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If you have divided down clock generated from main clock using some logic, then without generated clock constraint, the timing analysis tool may not know that the frequency of the generated clock is lower than the main clock. This will result in over constrained synthesis, where the logic using...
Power on resets -> system clock -> AHB clock -> AHB reset. AHB clock will be generated from system clock ( can be gated if no AHB traffic) and AHB reset will be generated from power on reset synchronously deasserted with AHB clock, so need AHB clock to release the reset. Software reset can be...
Yes, if three reset input to the block , then provide all three. Three reset serves different purpose.
Power on reset should be driven my main reset which is released after power up.
software reset should be driven by software accessible register. This reset is toggled only when software...
When setup check is moved using MC path of 2, the STA tool also move the hold check up, which is not desirable as it is over constraining the design. Hold is 0 clock cycle ( same clock edge) , so hold check up is moved back to same clock edge by specifying in MC constrain.
The standard cells usually support both posedge reset and negedge reset flops. I am not sure, if there is any specific reason, one would go with posedge reset vs negedge reset. Like FvM mentioned, it could be arbitrary design decision.
Re: Can anyone explain why are setup & hold of half cycle ssb are both freq dependent
In full cycle path with the same clock, hold checks for flop to flop path, are not frequency dependent because hold checks are calculated at the same clock edge for the launching and capturing flop. Whereas...
**broken link removed**
The original CGC cell is shown in the diagram above. If you replace with positive latch, during clock high period, the latch is transparent, and the clock output of cgc depends on enable signal. Therefore, if enable goes high in between clock high period, the AND gate...
If the CGC enable, which may come from combinational logic, goes high in between when the clock signal is high, it may potentially clip the clock pulse output of CGC if we use positive latch in the CGC instead of negative latch. This may produce variable clock pulse width.
How are you fixing setup violations? If you are shortening data path to meet setup check, I don't see why that will produce new set up violations. If the data travels fast, then fixing setup may produce hold violations .
Is your question related to timing analysis ? what do you mean by how to build a clock?
In SDC, you can define both mux input as a clock with their respective frequency. Then you have to run STA twice using "set_case_analysis 0 mux_sel" once and second using "set_case_analysis 1 mux_sel" to...
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