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i have a board with 8 led and my circuit output is a 32 bit vector.
my question is how an i write a ucf file and connect the output to the leds?
is it possible to break output and use a key to see out put continuously.
please help me.thanks
i want to use chip scope in ISE to see some internal net of my design.
my question is from the tutorial i saw there are two paths for this.
first one is chip scope definition and connection file and the second path is IP(CORE generator and architecture wizard).
i don't know what are their...
Re: lcd code for fpga virtex 6
thank you.
this is the code i find.
it was a verilog code and i change it to vhdl.
now i have some problem in converting it.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
entity lcd is
port(
clk, RxD ...
Concatination problem in port map in vhdl
i want to port map out_x=> mid
out is 32 bit std_logic_vector and mid is 16 bit std_logic_vector.
how should i do this?
i change it to thisout => (x"0000" &mid)
but i see this errorFormal "out_x" of mode OUT cannot be associated with an expression.
thanks.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use work.CONV_PACK_Top.all;
entity mux_top is
Port ( sel : in STD_LOGIC_VECTOR (31 downto 0);
mux_in : in T_2D;
mux_out : out STD_LOGIC_VECTOR (31 downto 0));
end...
could someone help me with this code?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter IS
PORT(
clk : IN STD_LOGIC;
out_c : OUT integer
);
END counter;
architecture behav of counter is
signal...
Re: generate vhdl netlist by ise
i do the flow but i am not sure i do part 4 correctly and i have error when i use the command in part 5
i have a code its language is verilog, when i synthesize it by ISE a file generate that its language is VHDL and its my code netlist.
now my problem change...
i have verilog code for a multiplier and i want to generate it's vhdl net list with ISE.
but idont khow how.
i use 1
Follow these steps:
1. Generate an NGD file for the core as follows:
NOTE: File can be EDIF or NGC. i.e. corename.edn or corename.ngc.
ngdbuild -p <part_type> corename.ngc...
count and signal_out are 2d arrays 32bit*32bit.
in this code i want to count the number of toggles of the signal sample(27) by count(27) and put the result in signal_out(27).
U_27 : counter port map (clk => SAMPLE(27), count(27) => signal_out(27));
but i receive an error which says...
FIR_IN is an array with 5000 data. each data in array is 16 bit."xn" is a 16 bit signal.
i want to put each of these 5000 data in "xn" one by one and use "xn" in some functions like sum and mult.because i want to repeat putting data of array in " xn" for 5000 times, i nead a for loop but design...
what should i use instead of loop to be synthesised in dc
i nead a good alternative for the loop which is being used in the below process
process (clk)
begin
for i in 0 to 4999
LOOP
xn <=(FIR_IN(i));
END LOOP;
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