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In Design compiler,how to transfer verilog file my.v into schematic view with tech my
Hi:
Anyone can Help me that in design compiler, how to transfer verilog file my.v into schematic view with technology myself,e.g.,tsmc,but not synopsis provide?
I add target library and link library with tsmc...
Re: How to define for "Freq" and "Noise" of vdc source in analogLib , cadence
thanks!
but how to use VCO_workshop? i have thought that it is a doc, but it seems like a software, when i unzip it.
BTW, what's the meaning of HTH?
---------- Post added at 03:24 ---------- Previous post was at...
How to define for "Freq" and "Noise" of vdc source in analogLib , cadence
when i do phasenoise simulation in VCO, i find that filling some value in "freq" and "noise" for example 1 and 1, the result of phasenoise entirely changed.
So i doubt what value in those box is reasonable. the doc of...
doing same simulation but on the different corner for example, make the key in the ADE for Normal, Fast, Slow to be rechoosed time and time by my hand and eyes, so I have to stay there to monitor.
Added after 3 minutes:
Thanks a lot !
scripting in cadence
because when I use cadence for example ADE to run simulation, some actions are always repeated and my hand is needed to control it everytime, so I want to study scripts to make the machine auto execute simulation. It is said that skills in cadence seem like to do it, but I...
what's the Vth of this process?
Vth of Nmos is 0.6~0.7V in generally, i know. so the spec 0.5V is too small.
in addition, your current maybe changed into low voltage type other than your diode connection.
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