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Re: VIA BLOCKAGE layer
Hi ,
That I understand.
What I didn't understand is why spacing is required between VIA1 and Via1blockage layer. The normal via spacing in the particular technology is 0.15. That spacing and the way how it is calculated is bothering me.
Please let me know if u have...
Hi,
Can anybody please tell me waht is viablockage layer. I encountered a section of a tf file that I am using as:
DesignRule {
layer1 = "via1Blockage"
layer2 = "VIA1"...
Re: Blockage Layers
hi
Can u please elaborate on the following tf file section:
DesignRule {
layer1 = "via1Blockage"
layer2 = "VIA1"
minSpacing = 0.22
}
What...
what is native mos devices
Hi,
I was looking for Native NMOS and I reached this thread. Can any one explain me the reason of low VT for the native NMOS transistors? If a transistor is being made in p-well then it will be NMOS thts ok with me. Is the reason for very low VT is very lightly doped...
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