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Recent content by montage2000

  1. M

    How to do the ac stability simulation of bandgap circuit?

    break the loop at sigle point, add stimulas and watch reponse at the other end
  2. M

    why V0/Vi is less than unity gain if RL is finite?

    because of internal resistor
  3. M

    How to do the noise analysis about Bandgap circuit?

    noise and bandgap use small signal snalysisy
  4. M

    Attenuators and Amplifiers

    can you put the figure
  5. M

    How to analysis the systematic offset of basic two-stage OTA

    every offset of MOS is divided by the gain from input to this MOS
  6. M

    how to calculate the phase noise of a oscillator?

    if the noise is not white, the result is wrong
  7. M

    Common Mode Level at Output

    not the average, but the midpoint of the effective output voltage
  8. M

    PLL : Issue in Phase Locking

    there is a lot of reasons , deadzone, charge injection, clock feedthrough and skew of UP/DN all can induce it , check these. Added after 10 minutes: balance everything in two clock path
  9. M

    PLL control voltage changes

    the phase margin is too small
  10. M

    high speed cmos current mirror?

    maybe active cascode is seful, that is use OP to boost output impedance
  11. M

    Cable characteristic, pre-emphasis and post equalizer

    you can see some paper in JSSC, they tell you how to do Added after 1 minutes: what kinds of equalizer,DFE or LE?
  12. M

    Preemphasis and equalizer in the SerDes design

    use transmission line as delay element, but the area is large
  13. M

    Spectre can do the noise analysis?

    noise analysis in spectre both of them can do noise analysis
  14. M

    Output stage of a comparator

    of course they should be in saturation
  15. M

    a question about PLL noise in high speed digital circuit.

    substrate noise is hard to isolated, except deep well
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