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Recent content by mona_patel

  1. M

    Failure of ATPG parallel patterns

    Can anybody tell me what can be the issue if serial patterns are passing and parallel are failing?
  2. M

    simulation debug for ATPG serial patterns

    Hi, My parallel patterns are passing and serial patterns are failing while simulation. Can anybody tell me what is the reason for this and how can we debug those serial patterns? Can anybody help please
  3. M

    simulation debug for ATPG serial patterns

    Hi, My parallel patterns are passing and serial patterns are failing while simulation. Can anybody tell me what is the reason for this and how can we debug those serial patterns?
  4. M

    Memory repair with efuse and bira

    can anyone share knowledge regarding efuse technology in redudancy analysis in mbist and how bira use fuse technology?
  5. M

    MBIST clocks synchronization

    Ya it's for ASIC so I have asked it accordingly in forum
  6. M

    MBIST clocks synchronization

    Hello, Can anybody help me for the following MBIST queries. At which frequency MBIST works? In functional mode which clock and in test mode which clock used? Can anybody tell me how clocks is synchronized between the controller in mbist and at the output side? As per my understanding we...
  7. M

    Fake IO in design for pattern generation in DFT

    Hi, Can anybody tell why we use fake IO definition for pattern generation(ATPG) in DFT?
  8. M

    INTEST, EXTEST and BYPASS modes without wrapper in DFT

    hi, I understand the concepts of core wrapping. I think we can also use INTEST and BYPASS modes with IP integration concepts. Can anybody have any idea regarding it?
  9. M

    INTEST, EXTEST and BYPASS modes without wrapper in DFT

    ok,thanks for your help. And what about BYPASS mode? One more thing I want to clear that Can we not use INTEST,EXTEST and BYPASS mode without using wrapper insertion?
  10. M

    INTEST, EXTEST and BYPASS modes without wrapper in DFT

    Re: INTEST, EXTEST and BYPASS modes without wrapper in DFT(design with IP) I know that, we can target coverage within IP of design---INTEST we can target coverage outside IP of design---EXTEST we can bypass IP by using BYPASS mode I dont know how can we implement this modes in scan so that we...
  11. M

    INTEST, EXTEST and BYPASS modes without wrapper in DFT

    How can we use INTEST,EXTEST and BYPASS modes without wrapper in DFT for design having IP to improve test coverage for ATPG. Is it affects any other things?
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