Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hello ,
well i am writing test case for a particular ip ....and whenever iam configuring the register i have to reset the reg model ....
Is it necessary to do that as in practical case user wont reset it every time he wishes to reconfigure ...
this is a simple example for a counter :
// TLM counter
// compiler: Visual C++ 2008 Express Edition
//
#include <stdio.h>
#include <systemc.h>
#include "tlm.h"
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace tlm;
using namespace...
Hello all ,
I have a few questions related to systemC TLM :
1.Well if we are using sytemC TLM modelling do we still require primitive channel in systemC models or it would be simply handled by TLM sockets ????
2.How should one decide whether there model is loosely timed or accurately timed ...
Hello all ,
I have a few questions related to systemC TLM :
1.Well if we are using sytemC TLM modelling do we still require primitive channel in systemC models or it would be simply handled by TLM sockets ????
2.How should one decide whether there model is loosely timed or accurately timed ...
well i want an system C model of LFSR (or a randomizer).....
as in digital it consists of a few flip flops with a few feedback path...
but in simple C++ it has a random(range) for it ....
I am not whether result fron both the cases will be same or not
as i am very new to systemC could any one...
could anybody help me why do we need parameters in generic design or is there any other way for generic design other then parameters .......
Any side effects of using parameters .....
I am only asking in terms of digital design ???
well i want to have a async reset which is active high on a block which is operating at posedge of sys clock..
my code is as follows.......always@(posedge sys_clk or posedge reset)
begin
if(reset)
......
.,,,
end(
my doubt is can we use both sy_clk and reset at posedge in order to fullfill the...
hello all,
i wish to design a sampler without using a faster clock(like 16x,8x or 4x)....can that be possible because i have limitation in producing a faster clock.....
Mohit Negi
A wish to design a module ...i have two methods one is writing the functionality of all sub components in same module(let the tool do all the work ) or making separate module for each sub component and calling it in the top module...
which approach is better ????
i have another doubt can we...
i have a very simple ques on verilog basic
module abc(a,b,c);
input a;
input [3:0]b;
output [3:0]c;
module abc(input a,input [3:0] b, output [3:0] c);
which of the above coding style would be better ??
hi,
sorry i could reply earlier i was going through the systemc code and i have a doubt that why have you used this:
const char* hdl_name() const { return "counter_module"; }
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
