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Recent content by mmz25

  1. M

    Simple verilog question

    Simulated with ncverilog... always @(posedge clk) begin a<=0; a<=1; end Time 0 a = x clk = 0 Time 5 a = 1 clk = 1 always @(posedge clk) begin a<=1; a<=0; end Time 0 a = x clk = 0 Time 5 a = 0 clk = 1...
  2. M

    ASIC FPGA VLSI in Dubai /UAE

    fpga jobs in dubai What is the kind of salary one should expect in DSO for 7+ yrs of experience in ASIC Verification ?
  3. M

    What companies in India offer Onsite opportunities ?

    I'd like to know What companies in India offer Onsite opportunities in the field of ASIC FPGA Design and Verification..?
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