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This is exactly my problem. I want to keep tracing the constraints imposed by the assertions (in HDL) at gate level. But after synthesis these net names are modified. How can I preserve my assertion constraints at gate level?
I am trying to do this for test purpose, since ATPG can only be done...
synopsys_translate_off
Anyone knows the tools that can synthesize the HDL to gate-level but preserve all the assertions? I need the assertion constraints at gate-level. I am new at design. Thanks
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