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Recent content by miryama

  1. M

    How to use SRAM out of FPGA?

    thanks hamed, i can solve it, write to SRAM and read from it but first sample don't write.
  2. M

    How to use SRAM out of FPGA?

    I can solve this problem finally :-P
  3. M

    How to use SRAM out of FPGA?

    Hello i write a vhdl code that write data in SRAM and read from it but i have problem in timing and output isn't true. I implement the timing of datasheet but can't. Who can help me؟!! thx:sad:
  4. M

    fft ip core in virtex4

    Dear syedshan i can solve this problem, ise can't generate several core Simultaneously but if in each step add 1 or 2 fft's to design show resources Surely . thanks Shan. i can't make an account on **broken link removed**
  5. M

    fft ip core in virtex4

    thx shan i I know this method but when i use several fft in design and synthesize it show me 350 warning and don't show resources that use. of course this program is only a test. again thankful:|
  6. M

    fft ip core in virtex4

    Hi i want to know how many fft core can use in virtex4(512 point,scale or unscale and in radix4) ? it means for all sources how many cores we can use? Who can help? thx.:idea:
  7. M

    problem( fir core in vertex4)

    i want to use a fir core that can decimate, input rate is 100M and output rate is 10MHz. but with my adjust doesn't work, Who can help me? :-|
  8. M

    setting of fir filter

    hi every body I want to use a fir filter in my design but can't adjust setting of it(sample frequency and clock input), i want use decimation 10,input frequency 100M,sample rate 10M .i want to know how it work my project is in vhdl. plz help me:cry:
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