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Not sure what frequency you are working on. For low frequency, you do not need matching network, except the DC blocking capacitor. What you need is to adjust 1/gm close to 50Ohm, and a choke to ground. You may also make use of the choke inductance to cancel out the parasitic capacitance of...
amplifier backoff
This is not a technique. i think this is a requirement. In some advance communications like 802.11, because of the modulation type that create some peak to average ratio bigger than one. To make sure we can deliever the linear output power, we need back off to account for...
I am not sure if i understand your requirement. If you want a simple unity gain buffer. u can use a OPAMP with the output feedback to the negative input of the OPAMP and with the signal input at positive input of the OPAMP
Re: what is STI ?????
STI = Shallow Trench isolation. It is used to isolate between different device.
Purpose of dummy to avoid(minimize) STI stress on the device, as STI will affect the device characteristic (Lod effect) which is not good, especially when you are doing matching like current...
fully differential amplifiers
for PSRR, put an ac source (Vmag=1) at your supply line. for CMRR, tied the differential input together and put an ac source (again, Vmag=1)
For both cases, use AC analysis, sweep frequency, and look at the output.
You will see the frequency response of PSRR and...
Re: LNA IIP3 simualtion
it depends on the application. This means you have to know the possible two tones that falls in band that create IM tones, or two possible out of band signal that the IM will fall in band. Given your information, it is hard to tell how to specify f1 and f2
IIP3 is...
Re: CML and Rail to rail
CML = Current Mode Logic
Rail to rail: typically to describe the voltage can swing to the highest supply voltage (for example, Vdd) to lowest supply voltage (for example, ground)
For variable capacitor, a simple MOS cap can do it. Simply change the bias at gate, the overall capacitance will change according to the bias. Some other advance variable capacitor like accumulation mode is also good
In most cases variable resistor can be done by MOS working in triode region...
Yes, becuase of the modulation scheme. EDGE use 8PSK which has a PAR of ~3dB. Given almost the same system, with the PA originally used for GSM, the output power for EDGE has to be ~3dB lower than GSM (Max power ~35dBm, which use GMSK with 0dB PAR)
Loop filter is used to filter out the unwanted spur and also suppress noise of the control line for VCO. This helps the overall phase noise. Typically the trade off is settling time, stabilitiy and noise requirement
You may go to the following website and look at PLL documents...
s-parameter spectre dc
For transient simulation, you have to set your n-port in your CDF to spline in the interpolation method. It is better if you can carefully modified your .s2p file such that there is a zero freqeuncy data
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