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Re: VHDL and TetraMAX
Yeah, thats what's frustrating. It works fine in Xilinx ISE and everything else I've opened it in, but when attempting to run ATPG on it in TetraMAX, it will only generate faults for the inputs and outputs. But if I use a verilog version that is the same exact structure it...
I'm currently trying to learn how to use TetraMAX to generate test patterns, but have come across a problem when using VHDL.
I have a simple benchmark circuit implemented in both VHDL and Verilog. When I run the Verilog design, TetraMAX creates a list of 50 faults, but when I use the VHDL...
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