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Recent content by milan.dalwadi

  1. M

    Physical Verification LVS

    Hello all, what is Layout Versus Schematic [LVS]? How to solve LVS in Synopsys ICC tool..?
  2. M

    After Routing step nd DRC problem

    Hello, Thanks for ur valuable reply,, but wat is drv..? nd i tried to rerun the detail route then DRC violation increased so now what to do to resolve both the violation DRC and LVS..[In ICC tool]
  3. M

    After Routing step nd DRC problem

    After Routing step nd DRC problem [synopsys toll] Hello All, what are the checks after Rounting...? and how to resolve the DRC violation afetr routing...?
  4. M

    Antenna Violations [checks after routing]

    Hello all, What is antenna violation effect ? How to solve antenna violations? Thanks-
  5. M

    Regarding Physical Design [Routing]

    Hello all, What is the difference between detail route and search & repair ?? What is switch box for the same?
  6. M

    About Clock Tree Synthesis

    Hello All, Pls Help me.. How to decide clock skew nd latancy during Clock Tree Synthesis..? How to meet setup timing in ic compiler from synopsis at CTS stage..??
  7. M

    About Clock Tree Synthesis

    How to decide clock skew nd latancy during Clock Tree Synthesis..? How to meet setup timing in ic compiler from synopsis at CTS stage..??

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