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Recent content by mike0426

  1. M

    why using non-ideal clock to simulate the circuit

    Thank you for your answers! But I still have a question, how non-ideal clock would limit driving capability? Can someone explain it in detail?
  2. M

    why using non-ideal clock to simulate the circuit

    I wonder that what's the difference between ideal clock & non-ideal clock(generate by osc). I heard that ideal clock may make us ignore some effect which using non-ideal clock would appear,but I'm not sure the reason and what the effect is. Hope someone know this can anwser this question...

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