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Recent content by mike.zhang

  1. M

    [SOLVED] New Cell Creation Using Skill

    create a new cell :deNewCellView("libname" "cellname" "viewname" “viewtype” winspec) example: deNewCellView("newlib" "test" "layout" "maskLayout" list(list(0 0) list(1200 800))) deNewCellView("newlib" "test" "schematic" "schematic" list(list(0 0) list(1200 800))) open a exist cell...
  2. M

    Circuit for dc voltage & current sensing

    How about ACS712 ? It's a current sensor with 2.1kVrms voltage isolation.
  3. M

    can i run old libraries that design virtuoso 5 in another edition virtuoso 6.1.4 ???

    No. Lib import don't work very well. You'd better apply for a new 61 Lib from foundry.
  4. M

    How to operate opamp on two different voltages

    Generate A lower power voltage for AMP.
  5. M

    start-up problem of bandgap

    u need a switch to pull down the gate of pmoses. the bandgap voltage or current is a good trigger.
  6. M

    range in cadence layer map file

    Hi rajaa2005 "metal drawing 13,10,18 0-63" three layers which number are 13,10,18 datatype from 0 to 63, will be stream to metal layer .
  7. M

    how to simulate LDO noise?

    click noise , set the frequency , set the output noise and input noise and run
  8. M

    ldo design operating in wide range supply voltage (2~6V)

    Hello Ella, Maybe u should choice the other process, in which the breakdown voltage is more than 6V.
  9. M

    How to simulate a PTAT circuit?

    IF ID1=ID2 AND R1=R2 RESULT VR1=VR2=VT*ln8 I think you should adjust the R2 to make the pmos and R2 work well.
  10. M

    which process do you use now?

    cmos,bicmos
  11. M

    Circuit for converting 110Vdc to 24Vdc

    110v to 24v dc Hi May be a AC-DC IC should be better! Regards
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