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Thank you all for your precious help.
Today I had the time to dig in a bit more, and with your insight I found and solved the issues. As it was pointed out, the problem was actually with the test-bench and the clock.
I draw a sketch of the problem to better illustrate it.
Basically in the...
Thank you for your answer,
You are right it never hurts to cover the basics. My test bench is in VHDL, I use ps as the default time units in the test bench, in simulation, in synthesis, and in pnr. The SDF is successfully annotated. As I mentioned, I even made sure to remove all the warnings...
Dear all,
I'm facing a problem with a post-pnr simulation that I hope you can help me figure out.
The design flow is based on the GPDK045 kit from Cadence. I use Genus & Innovus for synthesis & pnr, Modelsim for simulations, and I have compiled the standard cell library with modelsim for...
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