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Altera Cyclone PLL
Does anyone know if cyclone PLL is support the following:
Input clock : 32.4 Mhz
Output clk0 ; 32.4 Mhz (same to input and align to it)
Output clk1: 10.8Mhz (input /3, align to input)
In quartus II ver 2.2 (SP2) its seems OK , but in quartus II ver 3.0 (SP2)
I get from mega...
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