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I followed some tutorials to create symbol and schematic from Verilog but when I simulate the schematic I get nothing in the output, I checked the the circuit a bunch of times and repeated the whole thing also a few times but it still doesn't work
Its me again, I got the layout to work but now I have problems with the schematic, I import the synthesized Verilog code to the same library I'm using for the layout but the simulation is not working, I'm using Specter for the simulation, when I descend in the hierarchy in the schematic I don't...
When I export the gds in Encounter I add the Virginia tech stream out map, and in Virtuoso I use the .gds file exported from Encounter and I use the viginia tech stream in map, so I'm not sure what else I'm missing
Hi, guys its, me again. I'm still tryning to run a verilog code that I wrote its an OR gate, nothing complicated, when I synthesized it to use it in virtouoso, I wasn't able to find the transistors, what I did was write a code in verilog, synthesize it in Encounter and saving it as GDS2 3to...
that didn't work and I'm getting this:
The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file.
I wrote a verilog code, then I synthesized it in Encounter RTL compiler and imported the design in Encounter, I was trying after that to import it to Virtuoso as a DEF or GDS, the problem is that I can only seen the metals and vias in both Encounter and Virtuoso but not the transistors. I...
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