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question
i want to design the grantx signals as register output. But for a undefined length burst transfer, we can not predict the end of transfer, the grantx signals change always one cycle later than expected. for a fixed length burst transfer, because the master may insert a BUSY state...
Re: help for ahb arbiter
hi whizkid
question
i want to design the grantx signals as register output. But for a undefined length burst transfer, we can not predict the end of transfer, the grantx signals change always one cycle later than expected. for a fixed length burst transfer, because...
1 kb boundary in ahb
should i insert idle transfer to the end of each burst transfer?
if yes, how many idle transfers should be inserted?
and, should i insert idle transfer to the end of single transfer?
urge for your reply, thanks a lot
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