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Hello
Sorry i was not online, mee too i search in Google. But sometimes i have Lucky sometimes No.:wink: after i come here for Help.
Thnx Man.
Greetings.
I want to thank you a lot
:thumbsup:for time and help and advice.
I fix it, ;-). i make mistake in Code.
May i ask you one more question?
Do you know any Tutorial in Internet, to learn about FRAME BUFFER(how to design) in verilog.
Thank Man one more time.
Greetings.
Hello …
I am using Quartus 13.1
This is Video Test Pattern, normal i have to get the picture in vertical ,
but in this case i get in Diagonal the orginal picture…
I want to know is in counters (of does have to do also with TIMING).
Thanks you for help....
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Hi,
I did not...
helle everyone
everything ok.
can somebody help me?
in place to get this pattern test
part 1
| | | | |
| | | | |
| | | | |
--------------------
i get this one the same pattern but diagonal like this
part 2
/ / / / /
/ / / / /
/ / / / /
/ / / /
-----------------------
why i dont get...
thank you for time you lose for me....
thank you.
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hello
thank that you try to compile
but i still dont understand what is the problem
is FIFO small or i have small memory of luts in my fpga
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happy wekend to all
hello
i have 100gb and 4gb ramand dual processor 2.2ghz
but there is no problem, something have to do with font rom(I THINK), because when i remove the font_table is working direct i mean compilation but
not working, and i have fpga de0 develompent i think ram is 550kb and 4 pll ....
thnx
- -...
hello
i try to compile those files in quartus 13.1 web edition
so i let COMPILING for 5 hours and not done
what do you think? what is the probleme?
code is here https://gist.github.com/michael19788/bed63277945352fb84739c99f938b9d7
please can somebody help me?
thanks.
hi
no i just want to try add vga and keyboard, and i look for my self easy way to do in that way!
of one question man i look long time in internet books
i cant find one book wich explain complete computer with display and keyboard everything connected.
do you know any book?
thnx
good morning
i try to do the best with google translate!
sir, i cant come til the analysis and synthesis,i get error!
yes that is true i want to make quartus fpga library primitives.
that i want fpga library primitive from that source file mips.vhdl.
Sorry about my file i just find that...
hello thanks
yes i simulate with modelsim and active hdl
but active hdl you can make a block diagram you have all symbols of this file mips
and i dont use active hdl but i want also in quartus to simulate and to make all symbols from file and to connected together in block diagram from this...
hello
please can somebody tell me how to simulate this file in quartus 13.1
i dont know i get just error
this the mips processor from book design digital of computer architecture here is vhdl file https://files.fm/u/wph4x5ze
all mudules are in one file i dont know how to do it ?
thnx
yes that is true, but i dont understand all pin legend, for that i am searching tutorial to explain more in detail, because i am scare to make any mistake for example to put iniput to output in fpga and i can damage the fpga, like i learn from that cursus because i put all the pins from cpu in...
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