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Re: Analysis and Design of Pipeline Analog-to-Digital Conver
He is a professor at UT Dallas. You can go through his slides...most likely the book will have same coverage of contents....
Hello Everyone, I want to design a 4th order Butterworth LP filter of Sallen Key type. The 3dB frequency is 750MHz....can someone give me ideas, references, etc. to achieve this high frequency filter design
thanks
Hi All, I have a question related to Cadence....After i do the DC sweep simulation, I want to plot the variation of some parameter vs any parameter..the cadence won't let me choose this option. It plots "vs" the default swept value.
Eg: If i sweep W (width) of a device and now if i want to plot...
Hello all,
I need help in designing a very low noise Op-Amp (Single ended input and differential output) with 10MHz BW....what is the best architecture i can use??
regards
Hello all,
can someone tell me how to fix the order of Harmonic balance (eg: in mixer simulation) ?
frequency order:
order [1]:
order [2]:
because, the output power changes with the order so i do not know how to select an appropriate order...!!
Thanks
Hi trav1s, No that was not my question....suppose i am simulating a common source amplifier.... now you want to print its DC operating point.... one way is to use the drop down menu from Virtuoso ADE under results....the second way is to annotate the DC operating point of the transistor, there...
Hi,
While annotating the transistor for its operating point, i can display only 3 types of component display properties (eg, Id, Vgs, Vds or any other 3 types)... but if i want to display more than 3, say 4 or 5 such type of properties .... is there any way?
thanks
Hi, While annotating the transistor for its operating point, i can display only 3 types of component display properties (eg, Id, Vgs, Vds or any other 3 types)... but if i want to display more than 3, say 4 or 5 such type of properties .... is there any way?
thanks
Hi, I have this problem and would appreciate your suggestions....
I am building a receiver chain in 65nm CMOS process where my low-IF frequency (from a single ended output of a mixer) is 1MHz and i have to build a very low noise base-band amplifier....
1) any suggestions of making this...
Hi rakesh228, Was this relation (conversion loss vs LO power) "dB to dB", i mean with every increase in LO power (say 1dB) how did the conversion loss change?
regards
Hi, I have this problem and would appreciate your suggestions....
I am building a receiver chain in 65nm CMOS process where my low-IF frequency (from a single ended output of a mixer) is 1MHz and i have to build a very low noise base-band amplifier....
1) any suggestions of making this...
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