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If you're reading files, I assume that this is testbench (or non synthesizable) code.
That being the case, why all the code to generate a clock.
signal clk: std_logic := '0'
....
clk <= not clk after time_constant ns;
A lot of coders continue to write synthesizable code when it's not...
If you only want to do something once, just create a boolean variable and set
it's default to 'false'. Check the variable before you do your read. Then do your read or whatever, and then set the variable to true.
VHDL i.e.
...
read: process(clk,reset)
variable did_it: boolean := false;
begin...
It's not foolproof, but this tcl/tk testbench generator I wrote does the testbench shell pretty nicely. As I mention in the help function, if you don't like it, hey, you have the source.
Enjoy
Here's a tcl script that does command line synthesis for FPGA Compiler II or FPGA Express. Read the help screen to setup a few extra files (inc_file.txt and part_file.txt) the the script need to synthesize the design.
Mike
Uploaded file: **broken link removed**
vhdl testbench generator
Anyone interested in a single entity VHDL testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.
Uploaded file: **broken...
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