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Recent content by memsgg

  1. M

    International MEMS Forum Centre

    mems forum International MEMS Forum Centre www.memspub.com This is a new Forum of MEMS, please come here and share your ideas and experience here. Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon...
  2. M

    Question on noise simulation in Cadence

    divide output noise by gain, you can get the input noise... the gain varies with frequency
  3. M

    can we use battery as power supply to reduce noise?

    Normally, how much noise can the battery induce? Is it lower than signal generator power supply? Many thanks
  4. M

    Area for ESD protection diode

    calculate by leakage current and paracitic capacitor you can stand
  5. M

    how to simulate gilbert mixer in lock-in amplifier?

    lock-in amplifier howto I am designing a gilbert mixer for using in lock-in amplifier. The LO and RF freqency is same(10kHz) to generate a dc voltage to be measured, I think it is a simplest useage for a mixer, can any one tell me if I need to use PSS, PAC and Pnoise in cadence to simulate the...
  6. M

    Is ESD protection essential?

    I know the ESD protection is very important for chip safety, but the chip I will design is to sense very weak current(lest than pA), so the leakage of ESD protection circuit shoud be less than pA, do you know, normally, how much current is the leakage from ESD protection? If it is larger than...
  7. M

    Is ESD protection essential?

    I think the ESD leakage is in the range of pA, but not sure...
  8. M

    Is ESD protection essential?

    I just wonder if we must include ESD protection on every pad? In the low noise and low leakage current application, the input pad should be away from ESD protection, is it right? But is it safe from ESD? Does anyone know if the commercial opamp input has ESD protection? Many thanks Yong
  9. M

    about low noise pmos buffer design

    Do you mean I should choose the topology b? Can you please give me more explaination? Yes I will do the full layout. I have a 5uA current already in the layout. Thanks a lot.
  10. M

    about low noise pmos buffer design

    I plan to design a low noise pmos buffer, which need large input and output swing rang, I have two topologies, can any one tell me which one is better? or any other topology is better than these two? Many thanks 1. I have a 5uA current already in my design, can I use 10X current mirror to bias...
  11. M

    is post layout simulation obligatory?

    But I think the frequency is very low, 10KHz, so it is unnecessary to do the postlayout simulation, is it right?
  12. M

    lock in amplifier IC design

    ad630 lock in can anyone answeer it for me? thanks
  13. M

    Need help on Voltage output

    I am not very clear of your case, a picture is better. However, you can try to connect a buffer on the output node. good luck
  14. M

    why use a ptat or bandgap bias

    I have the same question, can anyone answer it? In specially, if a opamp's bias current is 300uA, can we directly use a current generator to connect it while testing? thanks advance
  15. M

    lock in amplifier IC design

    I plan to design a lock in amplifier IC to sense weak signal from noise, can anyone give me some advice or share some experience? I have no idea now. Many thanks Yong

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