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Hello,
I am trying to compensate an LDO across all corners.
My boss suggested me that I need to find a correct value for R3 and C3.
The picture below is the block diagram of the LDO.
My questions:
1. is there a way to find a correct value of R3 and C3 other than trial and error? so far, there...
Hello,
I am designing an LDO whose block diagram looks like the picture below.
The error amplifier is 5 transistor OTA with NMOS diff pair.
All the internal circuits are powered by the output voltage of this LDO, i.e., self powered, V4A and V4B are connected.
At SFF and SFS corners at Temp >...
I understand what you mean. Thanks.
I agree, some precision requirement is needed.
Thanks for the insights.
My supervisor suggested to use similar circuit but the control only come from either PMOS or NMOS, but not both, while the other side is connected with diode-connected MOS.
If I did it...
Hello,
My supervisor suggested me not to use the delay circuit shown below.
The reason is we cannot guarantee if ID of PMOS and NMOS to be the same.
While I completely agree with this statement, I still do not understand the relevant of it to the functionality of the circuit.
Even if the...
I want to model Voltage-Controlled Delay in VerilogA using absdelay(target_waveform, delay_control).
But somehow only the first value of delay_control that is used.
In other words, the delay is there but with fixed value.
Did I miss anything?
// VerilogA for Regulator...
Thanks guys for your reply.
And how can I define the range of the linearity?
Is there any more practical way that can be done in Cadence?
It is actually a current source injecting current to a capacitor which is suspected to be nonlinear.
I need to check the linearity of VOUT.
Let me know if...
Hello,
I need to find the range where the curve (red) is still considered linear.
For this I ploted the first (yellow) and second (green) derivative.
I also marked when the second derivative drops 60% (arbitrarily chosen) from its peak.
But I am not sure, whether this is a fair way to define the...
Ooops..honest mistake. I am not trolling and was not aware that the output impedance was multiplied.
I know regulated cascode for TIA and didnt thought it is the same case here.
I will derive the small signal analysis tomorrow.
Thank you!
The bulk is connected to -1.2V, that is not a mistake.
Here is the simulation when VBS of cascode transistor = 0V and VB of bottom transistor = 0V.
Still the results are not the same.
I usually use small signal formula to calculate output resistance (method 1).
But now want to find a simulation setup to measure it (method 2) so I do not need to input the expression of rout.
A good discussion I found from here and here.
I still do net get the same result between method 1 and...
I am simulating a CSA-Comp pair like in the picture below (Picture 1) and would like to use PSS and PNoise analyses to find the input-referred noise charge or equivalent noise charge (ENC).
But I got no noise result in the data browser and warning message "WARNING (SPCRTRF-15495): No crossing...
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