Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Melinda123

  1. M

    Verilog... is it good practice reset to high ?

    Hi, I have a (maybe silly) question : Suppose we have few counters in FPGA design... used to index some particular registers, memories etc... Explanation: Suppose we need to index zero element from some register...if we start to count after reset i.e. (suppose 5 bit counter) cnt <= cnt + 1...

Part and Inventory Search

Back
Top