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Recent content by mehrzad321

  1. M

    SDHC host ip-core for xilinx FPGA

    Hi all, In my project I need to implement SDHC host as a part of my design. My FPGA platform is Spartan6. Honestly I don't have any idea about how tough it would be. Anyone can help me finding an approved SDHC host IP-Core (preferably in VHDL). I also need to find proper linux driver for it (my...
  2. M

    dumping the JTAG signal generated by xilinx Impact tool

    Thank you mrflibble for your reply. would you please make it more clear what you mean by tcl/tk files for Chipscope? the only thing I know about Chipscope is its use for sampling internal signals inside FPGA.
  3. M

    dumping the JTAG signal generated by xilinx Impact tool

    Hi All, I'm looking for any tool, document, application note,.. you name it, for logging the JTAG signals generated by Xilinx Impact. Actually I want it for compare it against the signals generated by XAPP058 which is a software implementation of jtag master protocol. it reads in the .xsvf file...
  4. M

    Implementing JTAG protocol in embedded software or firmware

    Keith, Thank you, I'm looking into it.
  5. M

    Implementing JTAG protocol in embedded software or firmware

    Hi All, My board poses an Ethernet connector which I'd like to use it for configuring the FPGA configuration PROM and bypass the JTAG cable. My idea is to generate PROM configuration file (using Impact) then pass it through LAN cable to embedded CPU which is implemented inside FPGA. Then CPU...
  6. M

    Simulation with VHDL: How to create stimulus with Jitter?

    You must use functions in "ieee.math_real" library to generate random numbers in a limited interval.
  7. M

    VHDL code for LCD display

    lcd display verilog code for spartan 3a It is very easy to convert this simple code to VHDL format but if U are as lazy az me ;) you can search for some automatic converter by googleing it, it's a peace of cake to find a good one.
  8. M

    How to know if clock is toggling?

    you can simply detect rising edge and falling edge of a given signal by register it and then compare it with one cycle delayed version: if rising_edge(clk) then sig_1 <= sig; if (sig = '1' and sig_1 = '0') then --- rising edge of sig end if; if (sig = '0' and sig_1 = '1') then...
  9. M

    VHDL code for serial in serial out

    verilog tutorial, serial out Hi, Can you clearify your need? what kind of process you want to be done on input data? do you really want to just give serial data from one hand and put it outside with another hand? both input and outout are serial?
  10. M

    Urgent need for MT28F128J3 VHDL/ Verilog Contorller Please H

    HI, Is there any kind guy who can help me to find a VHDL or Verilog controller for Micron "MT28F128J3" Flash memory? I found VHDL controller for new Flash memory devices, from Micron Tech. website, But THIS DAMN device is announced as obsolete on Website. I really need it and I'm running out of...
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