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When I do post layout simulate the RC extracted version for the VCO it fails to oscillate for 8C built by 8 parallel C while in C extracted version, it works fine. so there should be something in interconnects of these 8 parallel C caused this problem. any suggestion?
I am using switch capacitor bank in my VCO design, with C,2C,4C,8C values. I used unit capacitor architecture, for example putting 4 Capacitors in parallel to make 4C value. Is it degrading the Q factor and should I use a single 4C cap value instead of it?
I am using switch capacitor bank in my VCO design, with C,2C,4C,8C values. I used unit capacitor architecture, for example putting 4 Capacitors in parallel to make 4C value. Is it degrading the Q factor and should I use a single 4C cap value instead of it?
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