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sir i am doing project in Canny edge detection and i need to implement my project in fpga board and displaying the same with help of VGA monitor.
my image size is 512 X 512.
please suggest which development board will be more suitable with less cost.
I am getting analog output from an output SMA Connector (J15) in stratix board.
From development board datasheet it sayys it uses a 1:1 transformer to couple the output to SMA.
Sir/Madam,
I am using a dac on stratix board to generate a triangular waveform.
Actually the DAC in stratix board is dac904. I have gone through its datasheet.
I hav designed as clock to dac is 100MHz and the input to 14 bit dac is an up/down counter of 10MHz.
But i get only a peak to peak...
Hi sir,
HDL files are shown with the different methods that i ded.
METHOD 1:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pulsein is
port(clk:in std_logic;
reset:out std_logic);
end entity;
architecture rtl of pulsein...
Sir/Madam,
I am trying to generate a low going pulse of 100ns and after 100ns the pulse must be HIGH.
I am using a clock of 50MHz.
Methods i have used so far but couldnot synthesize it.
1. Using a counter to count upto 5 and after 5 the reset pin goes high. it was simulated but couldnot...
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