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Recent content by mcdjnaja

  1. M

    Hierarchical design with SOCE

    Hi, thanks for your response. For the unclear part,I impose during the routing phase no level 4, 5, 6 (with createRouteBlk). But, after, when i generate the LEF corresponding to this block, I have an obstruct for the level 4, 5, 6 for the entire area of my block in spite of this level are not...
  2. M

    Hierarchical design with SOCE

    Hi, my explanation is not understandable or nobody has an answer ?
  3. M

    Hierarchical design with SOCE

    Hello everyone ! I am new on this forum. I am working on the design of a MPSoC including 30 cores of microprocessor. So, this design is hierarchical and i do a bottom-up place and route. First, I place and route the RAM and the cores of processor. With SOCE, the output of this place and route is...

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