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Hello,
I'm using createPlaceBlockage -box... command to blockout standard cell placement in a certain area in my floorplan for memory to be placed. The shape is not rectilnear (I'm using multiple createPlaceBlockage commands).
My question: is it possible to allow the actual blockage...
Thank you for the clarification. I believe my issue it that I have too many I/O pins for the area needed to fit the standard cells. When the IO pin placement happens based on minimizing routing, this results in congestion in certain areas. If the logical IO pins were spread out more evenly...
This is at the chip-level. I have some regions blocked out for memories. The blue layer is metal 8, and the highlighted square is one net overlapping with another net, both in metal 8. They are trying to connect to the pins at the boundary (yellow triangle). I don't understand why they are...
Hello,
At the end of my APR, I am getting IO pad short between two pins in one particular metal layer. This happens even after running ECO route and even though this particular location is not metal congested. I'm not sure why this happens. I can fix this manually easily, however I'm trying...
Hello,
I get the following "invalid" polygon error when reading in my LEF file. This polygon describes a port on the standard cell and therefore I cannot route to the macro because of this error.
#WARNING (NRFL-176) invalid polygon point list.
#WARNING (NRDB-733) PIN B in CELL_VIEW...
Is there a way in Cadence Encounter to iteratively optimize for the smallest dimensions that would perform the Place-and-Route without congestion?
I want to determine the smallest feasible area for the core and one way to do this is to manually try a certain floorplan dimension and if it...
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