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Hello
I want to make a data acquisition system using a micro-controller/FPGA, interfacing it with PC via parallel port. I was just wondering if I could get a sampling rate of about 1.5 Mega samples/bytes per second (assuming one sample is 8 bit long). I mean I am only concerned about the...
I have a set of instructions that I want to be executed for ever, while in parallel to this execution, I want MATLAB to scan for user input that I can use to pause/resume the execution of the set of instructions. Is it possible in MATLAB. Any Suggestions please.
Thanks,
Best regards,
Muhammad...
Hi!
I am looking for a Transparent Magnet for my experiments. I have googled it but could not found any commercial product. Is there something available.
Thanks,
Best regards,
Muhammad Awais.
Hello I am trying to do 2D convolution in MATLAB.
its easier to do it with conv2 function. I was wondering if I could do it like this.
computing convolution in x-direction and then in y-direction using linear convolion function conv in MATLAB, and finally combining them to obtain a same result...
Re: Verilog or VHDL
Hi!
I want to add up something. If I am not wrong you also asked as what software or development tools you need?
If you are working with Xilinx FPGAs then you will have to download the development and simulation tool from xilinx. that is Xilinx ISE 11 and thats free the...
Hi I am currently working with virtex 2 pro fpga and want to use the dual port ram, the problem I am having is that in simulation it shows right results while when I synthesize my program it does not work accordingly. I have varified this that the problem is only due to the use of dual port ram...
Re: Programmable frequency divider from 1 to 32 division fac
Hi andrew!
I dont know how far you are with your current design, but I had some helping material that I thaught to share with you so that you have more ideas to do with.
The attached file shows how you can make a exactly an odd...
vhdl not code
Hi!
I am new to VHDL, I want to know that is the following piece of code synthesizeable or not
process (x)
begin
if(x' event and x = '0') then
.....
....
end if;
end process;
Where x is any signal or input other than the clock. I am perticularly refering to the event statement...
Synthesizeable or not?
Hi!
I am new to VHDL, I want to know that is the following piece of code synthesizeable or not
process (x)
begin
if(x' event and x = '0') then
.....
....
end if;
end process;
Where x is any signal or input other than the clock. I am perticularly refering to the event...
bicubic interpolation
Hi! I am currently working with image down sampling. Can anyone explain the basic concept and idea of image down sampling using bilinear and bicubic interpolation.
Thanks,
regards,
Muhammad Awais
FFT Simple question
Hi!
I want to know that what does the term "fft bins" exactly mean?. I have searched for it but could not understand it exactly. That if for a discrete signal x(n) we take an N point fft, then FFT spectrum will have N frequency bins. Is it right or wrong. Please correct me...
Hi!
I want to know if there is some way to divide the input clock frequency by any integral factor e.g. a division of input clock by 3. I know its possible to divide the input clock freq. by powers of 2. But how about any other integer.
thanks.
regards
Muhammad Awais
HI!
There seems no reason of data loss. Well if you can put a pieace of code that can help to understand the problem.
One more thing try taking data on the next rising edge of the clock in process2, i mean instead of initiating process2 on falling edge make it a rising edge as well. then check...
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