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The voltage gain of an amp is Gm*Zout,
the bandwidth of the voltage gain is limited by the Zout as signal freq increases.
I wonder whether the Gm also has 3dB bandwidth or not.
And If Gm has 3dB bandwidth,what element cause it?
In voltage mode operation,the impedance(R parallel C) of a node will decrease as the signal freq increases with the current(I) flowing through unchanged.So according to V=ZI,the voltage at that node is degraded 3dB/dec at the signal freq at 1/RC.(assume the node has domonant pole)
But how about...
why the bandwith of current conveyor is larger than opamp?
I heard that the bandwidth of a current conveyor is higner than opamp because it work at open loop.I don't understand what's the reason.
The open loop 3dB BW of an opamp is 1/RoCo,where Ro and Co is the res and cap at the output node...
Re: Why the stable supply voltage is "shaked" after connected to the testing board ?
The testing board only contains an op amp I want to test and some I/O ports(SMA,header),and all the inputs of this op amp are connected to ground.
Re: Why the stable supply voltage is "shaked" after connected to the testing board ?
There is no regulator on the board,I connect 1.8V directly to the header. And I will check the rating current of the power supply.Thanks for your advice.
Re: Why the stable supply voltage is "shaked" after connected to the testing board ?
About 60mA is needed for my circuit,and what is the rating of power supply?
Why the large amount of current taking from power supply can make this effect?
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The supply current is about...
Why the stable supply voltage is "shaked" after connected to the testing board ?
I used a power supply to supply 1.8V as the Vdd of the tested-circuit,
after I connected 1.8V to the Vdd pad of the testing-board,
the originally "clean" 1.8V began to shake.
The phenomenon can be improved by...
So dust and moisture can be model as a very large resistor to gnd, input current can be viewed as flowing through it and produce a large voltage change at input terminal?
But if I design the input stage without diode connected,the input
can be model as an open (as T model expresses),there is no
cap or resister to ground at the input to let stray charge estabilish
a voltage at input .
Re: Do I need to make a DC path at the input of an op amp?
why the input voltage to the op amp could drift up and down randomly?
there is no current flow into the gate of a MOSFET,the gate voltage is independent to current,why C1 can be charged?
I've heard that a DC path is needed
at the input of an op amp,or the op amp
won't be functional because there is no
path for the input bias current.
(in the image below,R1 provides a dc
path for input bias current)
But if I use MOSFETs to design an op amp,is there still input bias...
I have another problem.
how to bias the output to 900mV if both of the inputs are connected to input signal coupled through a cap?
Can I still add a DC voltage source to +input to bias output?
the voltage of +input = -input,but -input is connected to output through a negative feedback resister R2,why the output level doesnt equal to (Rout/(Rout+R2))*900mV but equal to 900mV?
should the output reference input connect to V+?
why output dc bias equal to the bias of +input?
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