Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I installed a virtual machine. My virtual machine is XP, I am using matlabr2010a and Xilinx 13.1 ( System Generator 13.1).
I get this error when I do Hardware CO-simulation in Simulink. I can play the simulation , but when I generate Hardaware co-simuluation I get this:
ERROR: A license...
I have installed Xilinx ISE 12.1 and Modelsim_dlx_6.5e. I have compiled the xilinx's libraries for this simulator MODELSIM- DE ( for the 'mti_de' simulator) but the ISE project navigator doesn't recognize this simulator. When I change the design properties in project navigator to MODELSIM-PE...
Hi,
I have a design in System generator and it works OK when I generate HDL code in ISE
I am getting the following error in Modelsim when I I run simulation. Can anyone help me please.
**Fatal: (SIGSEGV) Bad pointer access.
#time 0 ps Iteration 0 Process:/...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
