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Recent content by masterpb.mail

  1. M

    No state transition in verilog code

    Thanks for the reply. I had simulated using Vivado simulator by forcing the inputs. So the test bench is not used. Is it possible resolve without test bench? I need the state transition to happen from ST_IDLE to next state ST_DATA_TX. If spi_wr_en is enabled then it should proceed to next...
  2. M

    No state transition in verilog code

    Hi I am writing SPI master for an ADC communication. I wrote the verilog code as shown but when I simulated using Vivado I found no state transition is taking place. Would anybody help me in it? module spi_master # ( parameter CLK_DIV_FACTOR = 5'd4 ) ( input adc_clk, input clk_in...
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