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Recent content by master.ro

  1. M

    Looking for Specman training labs

    Re: Specman labs HI MFM Did you find the training labs? I need them too! Thanks!
  2. M

    How to begin learning specman and e language ?

    specman evc basics Hello friends! Where can I found Design Verification with E by Samir Palnitkar? Can you give me a link or upload the book here? Thank you!
  3. M

    Floorplanning and Place n Route Information Required

    Hello! Do you have some courses for a beginner in floorplaning and place and route? Thank you!
  4. M

    function of "signal" in VHDL code.

    Hello! Signal count_motor from your code is a counter.
  5. M

    Problems with clock synthesization in VHDL

    Re: clock synthesization Hello! It' illegal to write if (bup'event) then state<= next_state because the synthesizing tool does'n know which type of flip-flop to implement. It doesn't exist a flip-flop which work on the both fronts of the clock.
  6. M

    What does 256 * 2 Mux 8 mean?

    Re: 256 * 2 Mux 8??? Hello! First you have to learn what is a multiplexer: A multiplexer is a device that selects one of many data-sources and outputs that source into a single channel. This sounds ambigous for me and I can not answer. Mux 2 - is a mux with 2 data inputs ,so it has 1...
  7. M

    How to write decimal numbers in VHDL?

    Re: beginner question Hello! You can use two registers: - one for the decimal part of the number - the other for the integer part
  8. M

    How to define VHDL registers in IOB

    Hello friends! I'm working to a design with registered outputs and I want to map (pack) the flip-flops in IOB flip-flops. Please tell me how to set up Xilinx fot this! Thank you!
  9. M

    What is timing closure ?

    Re: timing closure So, timing closure its the same thing with static timing analysis? Thanks!
  10. M

    Where can I find some information about clock tree insertion?

    Where can I find some informations about clock tree insertion? What tools I have to use?
  11. M

    What is timing closure ?

    Hello What is timinig closure Can you upload some documents or give me some links about timing closure? Thank you!
  12. M

    Does anyone have been on INFINEON interview?

    Re: INFINEON Hello research235 The post is for middle-level experience. Thank you!
  13. M

    Does anyone have been on INFINEON interview?

    Re: INFINEON Hello! Can anybody tell me how is the interview for FPGA Design Engineer and Digital Design Enginnet at Infienon? Thank you
  14. M

    How to constraint clocks in Quartus?

    Re: clock constraints Hello friends! What is ripple clock ? Thank you!
  15. M

    How to implement 1 to 4 demultiplexer in VHDL

    demux in vhdl Hello ! I think that the code posted by nand_gates is a mux not a demux. A demux has 1 input and 4 outputs and the input is connected to the output selected by selection.
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