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Hi , In my Design I need a Ram that its length is 80*32bit , when i simulate it whit Isim I get this unending elaboration field , but when I decrease its length it works , any idea how could i solve this issue ?
Thanks .
I want to design a processor that one part of which should be like this
W(k)=Pre_W(k)-3*W(k-1)
pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7
and my arithmetic operations are all floating point so i should port map them which i cant use process , to perform this I write the code...
by doing that my code is like this
for j in 0 to 7 generate
for i in 0 to 7 generate
s74:multiplier port map (a =>z1(i),b=>w1(j),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(j),clk => clk,result =>pre2(i));
s76: adder port map (a =>pre1(i),b=>pre2(i),clk =>...
s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
s76: adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result...
s74:multiplier port map (a =>z1(i),b=>w1(0),clk => clk,result =>pre1(i));
s75:multiplier port map (a =>z2(i),b=>w2(0),clk => clk,result =>pre2(i));
s76: adder port map (a =>pre1(i),b=>pre2(i),clk => clk,result =>pre3(i));
s77:multiplier port map (a =>pre3(i),b=>pre3(i),clk => clk,result...
Then what should i do in order to repeat the generate for several times ,?
if after finishing the generate one signal changes the generate will run again ? for example the generate belows finishes for the first time if i update D(i) , the generate will start again ?
for .... generate...
I want to design a processor that one part of which should be like this
W(k)=Pre_W(k)-3*W(k-1)
pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7
and my arithmetic operations is floating point i should port map them using components .
thanks .
I want to design a processor that one part of which should be like this
W(k)=Pre_W(k)-3*W(k-1)
pre_W(k)=∑x1(i)[x1(i)*W(k-1)+x2(i)*W(k-1)]^3 i=0 to 7
and my arithmetic operations is floating point i should port map them using components .
thanks .
HI , is it possible to use a generate statement inside another generate statement ?
here is my code but my pre1 and pre2 types are undefined .
gen15:for j in 1 to 7 generate
gen12:for i in 0 to 7 generate
s74:multiplier port map (a =>z1(i),b=>ww1(j-1),clk => clk,result =>pre1(i)); -------...
Whenever I attempt to launch ISim from the ISE design tools, I get a prolonged "elaboration" message followed with an error as shown below:
"ERROR: The simulation failed to launch for the following reason: Failed to communicate with child process. Please shut down ISim and retry the...
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