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Recent content by MaryF

  1. M

    Separating grounds in analog IC

    Actually, I need them to be separated in real life !
  2. M

    Incomplete nets (2 sources)

    Hello, It seems that these opens are nothing but the 2 source fingers of the same MOS. I am connecting these sources manually with M1. However, Connectivity check against source gives incomplete nets: Open on net 'Vdd' between: - InstTerm of terminal 'S' of instance 'MP0(0)' - InstTerm of...
  3. M

    Separating grounds in analog IC

    Hello, Is there any way to separate grounds in an analog IC. I made gnd_x ( ; x = the block number) pin for each block in the circuit but since these grounds are connected to the guard rings of nmos s and that nmoses are built directly in the substrate, I get shorts involving these ground nets...
  4. M

    Pdiff guard ring around nmos4?

    Hello, Is it possible to connect a pdiff gard ring around a NMOS4 to a potential different from ground? I tried it anyway and have gotten this DRC error: "VART MIN_Element Rule : vart min length = 2.0" besides that of a "BAD_NWELL_WELLTAP_MULTICONN_ERC" I appreciate any suggestions ... Thanks
  5. M

    How to set the limit of probed shapes in virtuoso Layout GXL?

    Hello, When editing a group of pmos surrounded by a MPP guard ring in the pane style I get a warning *WARNING* (GE-2190): The current probe is a limited probe and has reached the maximum number of probed shapes (1000). This may lead to an inaccurate probing display. And then All GRs are...
  6. M

    Layout GXL MPP GRs editing, max number of probed shapes reached

    Hello, I am using nmos4, pmos4 in the layout as well as in the schematic but it seems that the layout doesn't consider the Bulk terminal! I noticed that if I used the by default GR that comes with the nmos4 or pmos4 parameters, it will be considered as the Bulk terminal even if I don't check...

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