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You can find manual by synopsys' application engineer.
Others you should understand basically theory about PrimeTime, then you can write some tcl file about PrimeTime for your circuit and analyse timing of your circuit base on your tcl file. If you think that timing is not...
If let your circuit must meet timing and function of timing after P&R, you have better do clock tree synthesis. It was done by CTS tool.
logic synthesis is process that translate RTL description to gate netlist.