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Hmm. I must be really confused. I thought when you instantiated two modules the wires are automatically connected. Like so:
ram #(.RAM_WIDTH(8),.RAM_ADDR_BITS(5)) ram(
...
.ram_addr (ram_addr),
...
spi_slave spi(
...
.addr (ram_addr),
...
Ugh. Having another weird problem.
I am trying to test my newest SPI code and RAM from my top module. My top module instantiates both something like this:
module espSID_top(
input clk, // 20MHz CPLD clock
input rst,
output led_d1,
output led_d2,
output sid_clk, // 1MHz...
Quick question, besides this code being horrible:
// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr; always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge =...
Thanks again, this stuff is so useful to me. I learn best by "doing" and to have feedback on the crap that I've done really helps. I knew there was a better way to keep track of the reg_cnt, I just couldn't brain it in the moment :) Your proposal to use the upper 8 bits seems like an elegant...
Thank you!
I am also getting a very puzzling message during generation:
WARNING:Cpld:1007 - Removing unused input(s) 'sclk'. The input(s) are unused
after optimization. Please verify functionality via simulation.
How the hell can sclk be "unused" it's clearly relied upon in my design...
Hello again.
Ok so I have done some work on the spi slave / rom code. I converted all my assignments to non-blocking, which required me to rethink how I was doing things -- thanks to everyone for the help. In my test-bench it seems to work, but I was wondering if you fine folks could give it a...
Ok here is a snippet of my code, I got confused here with blocking/non-blocking.
The code first shifts in a bit from the MOSI line, then adds to the bit count, then I test to see if I have received a full 8 bits.
I figured that it HAD to block there because if I didn't ensure that the...
Hey ads-ee I appreciate the feedback. As I said, this is literally my second time working with programmable logic devices and Verilog. So of course the code is awful ;)
Your insights are helpful, I will clean up as best I can according to your advice. I am having a little trouble with the...
Hello,
I am currently working on a project with an old C64 SID (Sound Interface Device) chip. I'm using a Xilinx SC9572XL CPLD along with an ESP8266 acting as SPI master. The CPLD performs clocking of the SID, as well as conversion of the SPI data to the SID's address and data lines. While the...
Yah, I'm struggling to measure the actual currents as I don't have the equipment. I have a Mini-DSO and a digital multi-meter, but with pulses so short I don't know how I can figure out what the real world values are here. Any ideas?
Thanks again for the advice!
I'm using a 5v 2A power source for the LED, a wall-wart. Should put a capacitor somewhere near the LEDs? Eventually I will use 3xAA to power this, which should be able to provide more than enough current (it seems that they are capable of well over 2A). So, I guess I wouldn't need a capacitor in...
What do you consider a commercial product? I bet you the TV-B-Gone has sold more units than many "commercial" products, it's commercially available at dozens of web sites. And the people that designed it are EEs that I believe know what they are talking about. At least, they seem to be highly...
I'm no expert, but I have read many opposing viewpoints on the matter. If you have a sec read the TV-B-Gone design notes page I posted up above, I trust the people that designed that thing and they didn't use one. My TV-B-Gone has been working for a couple years, totally fine.
Doesn't the...
Hey folks,
I'm designing an IR remote that can be controlled over the Internet using a Raspberry Pi and LIRC.
Since the Pi GPIO is 3.3v, and you're only supposed to source a max of around 18mA from each pin (or 50mA @ 3.3v total from all pins) I need to use something to give the TSAL7600 IR...
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