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Hi,
So I need to make sure a MOS Cascode along with other devices in one (vertical) arm of the circuit lying between VDD and GND doesn't collapse under all corners.
For this i usually make sure the VDS (or the VCE in Biploar) doesnt go below say 250mV (or about 300mV in Biploar) in a nominal...
Hi Prashant,
Sorry the late respone.
I had used this command way way back. so not really sure how to answer your question appropriately.
The overall box around a particular layout design will be a rectangle with say coordinates as [(x0,y0) , (x1,y1), (x2,y2) , (x3,y3)] , where x-axis is the...
Hi Paddy,
Well i had a look at the schematic and I had a quick doubt. It seems that the point 7 on the circuit wants to go at 2.3V and -2.3V depending on the input potentiometer at 10k (you have maintained Point 1 at 2.3V).
So if the output of the OpAmp , point 7 , isnt being allowed to go to...
heres what i found going through cadence Fourms :
For a MOS transistor, the individual noise contributors are
fn, id, rs and rd.
-fn is the flicker noise
-id is the drain-source resistance thermal noise
-rs is the source parasitic thermal noise
-rd is the drain parasitic resistance...
haha, yes. I was thinking about that, but didn't think it all the way through to flattening it. should def work.
Thanks.
---------- Post added at 13:39 ---------- Previous post was at 12:11 ----------
by the way , i got a reply from a guy working in Cadence (Andrew Beckett) in their forum as...
I have made a layout structure consisting of 20 to 30 smaller components plus additional metal paths and pins. This was made as a revision to an older design and after a lot of changes and therefore the origin is not at 0,0.
QUESTION : How do I move all the components w.r.t each other to the...
Multi-Fingered capacitors would mean arranging +ve ref plate and -ve ref plate alternatively ,as in, the matching of the transistors. I am trying to find material on Multi-Layered capacitors, i.e., using Layer-1 as +ve ref plate and Layer-2 as -ve ref plate, or rather multiple capacitor plates...
I'll give u an example from a code i had written a while back. Note these both are abstract form from two different files :
//Eg for SEQUENTIAL LOGIC in Verilog
always @(posedge clock or negedge nReset) // check if you can make States
if (!nReset)
begin
DiceValue <= 1; // using <=...
i dont have any specific book in mind, but one good book for CMOS VLSI is
1. CMOS VLIS Design , A circuits and Systems Prespective by Neil Weste and David Harris
2. Digital Integrated circuits, a design prespective 2nd Edition (i forgot the author) - quite exhaustivly covers for inter...
**broken link removed**
the last section is the CMOS Based Gilbert multiplier. I apparantly came across the same paper and found this nov 2005 link of urs. hope it helps.
I am aware of the pdf book requests and stuff is banned here. no, this isn't one of requests.
but there isn't much material on Multi Layer Capacitors or multi fingered capacitors or stacked capacitors on the net. apart from a lot of patents on that subject which make a very tiresome and not...
thanks DarkCrusher,
on one hand, i couldn't write the steps since this report wasn't meant how to operate the cadence design kt, but rather how to use the tools and features to develop a butter worth filter. but on the other, like you (and few other people with whom i have shared this)have...
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