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VHDL DOES NOT allow division.
you can use little tricks like shifting the binary word a number of places by adding zeros to the left, but it would only be dividing into powers of two, and I don't want to do that.
Another option would be to implement a state machine and perform the division...
I have a digital signal between 0 and 65535.
I want to get a digital signal between 0 and 500.
In theory it would be necessary to divide by 131, but vhdl does not allow division, and since 131 is not a power of two...
Hi,
The samples have a size of 16 Bits (2 Bytes) each. If the register has a size of 64 Bits, it is because it has received 4 Samples. They are saved by the shift register, accompanied by a write flag. They come from a RAM memory controlled by a state machine.
Hi,
Filtering has to be done...
Here is the design that I have to do.
I have managed to have a shift register that "samples" every 8 kHz, and warns on each sample with a flag.
I must perform a PWM modulation at 200 kHz and then filter the message in a low pass filter that is integrated on the board.
The frequency of the...
Ok, I understand that by that logic, with a sample rate of 8kHz and a PWM of 200kHz, I get 25 discrete levels.
My "triangular signal" would be represented with 5 Bits, and would count from 0 to 24. My question is: If I have samples of several bits (64 Bits p.e.), which vary between 0 and 1, at...
Implementing a triangular wave in VHDL is not that simple, is it? I was thinking of making a square PWM, but I don't know how to mount the modulating wave on the carrier in VHDL
Hi everyone, I'm doing an electronics project, and I'm one step away from finishing it.
The situation in which my work finds itself is as follows:
I have a set of digital data (Audio) of 16 Bits each sample, which are sampled at a certain frequency, with its corresponding flag between samples...
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