Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by manjunath_crl

  1. M

    Calling VHDL code in Verilog Code

    Dear Sir, I am calling in my program like checkclock chekclk(.CLKA(CLK_INPUT), .GLA(FREQ1); it is giving error as FREQ1_C not driven. please help me solve this promlem.
  2. M

    Calling VHDL code in Verilog Code

    Dear Sir, I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.

Part and Inventory Search

Back
Top