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Dear Sir,
I am calling in my program like
checkclock chekclk(.CLKA(CLK_INPUT), .GLA(FREQ1);
it is giving error as FREQ1_C not driven.
please help me solve this promlem.
Dear Sir,
I generated PLL block using Libero VHDL code in smartdesign option. As individual PLL block it is working. I want to use this VHDL component in verilog code. How to use those components in verilog code.
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