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Recent content by manishpatkar

  1. M

    VHDL coding techniques

    Re: vhdl coding techniques my first post is a part of the second post.. i want to implement dco(second post with diagrams) , i could implement if i could use a way to delay it so asked the first post(on how to delay inside a process)... i am not able to code to get the desired output of dco...
  2. M

    VHDL coding techniques

    Re: vhdl coding techniques tff is the output of toggle flipflop with T=1 that we used as a input to test for now! so basically this for DCO for a adpll .. In our code we ae trying to generate a tff_new which changes due to carry and borrow inputs. just to make things clear i have attached a...
  3. M

    VHDL coding techniques

    Re: vhdl coding techniques ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11/13/2017 04:17:10 PM -- Design Name: -- Module Name: dco - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: --...
  4. M

    VHDL coding techniques

    Re: vhdl coding techniques we have a idc clock , tff flipflop(half of the frequency of idc) and a carry signal which gets high with certain offset. I want to geerate a new tff signal(tff_new) such that 1. if the carry signal goes high when tff=1 , the tff_new would be inverted wrt to tff next...
  5. M

    VHDL coding techniques

    inside a process how to wait for a rising egde or a falling edge ? or can we wait for certain fixed time ? eg. process (IDC) begin if(rising_edge(IDC)) then if(rising_edge(C)) then if(Tee= '0') then wait until ??; end if;
  6. M

    Logic -to_vhdl code for Increment decrement counter DCO

    i am trrying to design a DCO for adpll based on increment decrement counter. i am able to understand what to do but can't convert logic into vhdl code.. i have attached my reference for implementation and the partial code along with tflipflop that is being used: once carry is set high ,need...
  7. M

    kcounter loop filter

    i guess the code is working fine now! (let me know if theres still something faulty :))
  8. M

    kcounter loop filter

    yeah sir, i gave a clock for reset and the carry seems to be working!:) , but the borrow is propbably faulty! is the logic for kcounter loop filter correct ?
  9. M

    kcounter loop filter

    sir, reset given forced value 0..no change
  10. M

    kcounter loop filter

    i simulated without a test bench, gave two clocks for clk(kclock) and up_down.. borrow is always high in the simulation, it needs to change , idk what went wrong
  11. M

    kcounter loop filter

    i have written a code with k=8 , but it doesnt seem to work . i used the following in the paper for the logic here is my code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- the value of k is 8 entity updown is Port ( clk: in std_logic; -- clock...
  12. M

    kcounter loop filter

    i am trying to code adpll on xilinx vivado , i am not ble get the logic for kcounter loop filter! if someone can help me atleast with the logic or code, it would be really helpfull! my pfd code is here ---------------------------------------------------------------------------------- --...
  13. M

    Error while running simulation in the vhdl code using when else

    i was just practicing basics in vhdl with vivado. i wrote a simple when else staement , the synthesis worked perfectely but when i ran behavorial simulation i got following error ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors this is what i found in the Tcl console...
  14. M

    [SOLVED] Need adpll , vhdl basics sources

    1. where to learn vhdl from? (i have installed vivado , i understand how to code basic gates , flipflop ... i have to implement adpll so need to study related stuff) plz post links etc of good sources. 2. if i am building adpll , should i build it has one block or connnected blocks ?
  15. M

    vhdl codes for adpll-plz help

    we built a simulink model from various papers that we found on various papers Blocks for each components built using simulink. Phase detector implemented as EXOR, PFD and DTDFF. Loop filter implemented as K -counter LF DCO implemented as Increment-Decrement Counter. how do we build it for any...
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