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Recent content by Mamdouh

  1. M

    error in hspice using tsmc 65nm

    when i used the nch_25 model in hspice in tsmc65nm technology i found an error **error** Undefined parameter or function definition par1fn_mc for fn_dice_svtn. Please e nter a defined name. here's my code please help
  2. M

    hspice scripting language

    can i use any scripting language like tcl in hspice ?
  3. M

    converting vcd to saif

    before starting the simulation and after loading the file write this line in the command line power add /* this will report power for all nets in the design or you can use pwer add /top/* this will report power for all nets in the top file ( assuming that the top file is named top )...
  4. M

    What's the main difference between clock jitter and clock skew ?

    what's the main difference between clock jitter and clock skew
  5. M

    library setup time and hold time

    on reporting maximum delay in Synopsys DC a library setup time is added to the data required time i dont know what exactly is the library setup time and library hold time and how they are calculated so any one can help plz
  6. M

    reading saif file in synopsys DC

    my proplem is when reading saif file when i used read_saif -input tx.saif -instance_name topFILE -unit ps the output is 8 uW and when using read_saif -input tx.saif -instance_name topFILE -unit ns the output is 8 mW i use tsmc90nm design kit and written in the saif file (time scale ps) so...
  7. M

    converting vcd to saif

    yes i resolved my proplem but i didnt use vcd2saif i natively created saif file from MODELSIM simulator
  8. M

    reading saif file in synopsys DC

    on reading a saif file in synopsys dc a time unit is set the question is this unit is set for which time ????? the saif file contains (timescale 1ps) shall i make this time unit "ps" as said in the saif file???????? when i made that the dynamic power = 8 uW but the dynamic power before...
  9. M

    max capacitance violation in DC

    you mean to tighten my maximum capacitance constraint (to put maximum capacitance constraint less than that in the library ?
  10. M

    What's the default duration of the toggling in power analysis in DC?

    if i dont load the saif file (annotate switching activity) for my design the default value of the toggling rate is set for the nets but the saif file also provide the duration so what is the default duration in other words if i didnt annotate switching activity for my design in DC what will be...
  11. M

    max capacitance violation in DC

    how can i fix small max capacitance violations in synopsys DC
  12. M

    fix hold time violations

    yes it helped very much thanks
  13. M

    fix hold time violations

    can you please explain more ??!!

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