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Recent content by malolo

  1. M

    why we need binning in BSIM model?

    https://www.edaboard.com/threads/169607/
  2. M

    should i use logic salicide process?

    Hi all, are there general rules as to what kinds of process suits certain types of circuit? say, for example, is it appropriate for me to design ADC using Logic salicide process ? thanks, steve
  3. M

    threshold voltage in ibm 0.13um CMOS process

    hi all, I'm checking out threshold voltages in ibm 0.13um CMOS process, and found that, for NMOS, VTH0 = 0.0449539. while for PMOS, VTH0 = -0.2185202. I understand second order effect would affect, but isn' VTH0 too small for NMOS? any clues? here is the link: MOSIS file...
  4. M

    vdd, gnd missing in pdk

    Hi all, this question may sound silly, but I coudln't find vdd and gnd in the new library (ibm), does it normally come as part of the pdk? any clues? thanks, Steve
  5. M

    differential output to single ended output

    Hi, I'm just wondering if anybody knows how to convert differential output to single ended output in IC ? thanks a lot,
  6. M

    CMOS output, what does it mean specifically?

    CMOS output Hi, I encounter the term "CMOS output" in comparator design, what does it mean specifically? thanks,
  7. M

    On op-amp output noise

    Hi all, I'm wondering if anyone could clear some issues i have on op-amp output noise. Seems total output noise would have a KT/C form (with coefficient), and C is the load cap. therefore, a general rule to reduce total output noise is to use large loading cap. however, from textbook, if...
  8. M

    Cadece default simulator

    Hi, does anyone happen to know how to change the default simulator (in Virtuoso Analog Design Environment) from hspiceS to spectre? thanks! Kev
  9. M

    NCSU technology file, model libraries for resistor, caps?

    Hi, In NCSU technology file, the model library only has transistor model, is there or should there also be model libraries for resistor, caps etc? thanks, Kev
  10. M

    isolated ADC chip for communication system

    Hi, I'm just wondering in what communication system is isolated ADC chip used? anybody has any idea? thanks, Kev
  11. M

    testing bandgap reference

    anybody ever done testing bandgap reference?
  12. M

    testing bandgap reference

    Hi all, I have a few questions on testing of a bandgap reference chip, 1. how do we set the environment temperature? by placing the chip on the hotplate?? 2. what instrument do we use to measure the output voltage? thanks a lot, -Kevin
  13. M

    question in postlayout simulation

    thanks anyway Erikl, i'll keep looking
  14. M

    question in postlayout simulation

    LVS run is successful, cell with extracted capacitors is shown below.
  15. M

    question in postlayout simulation

    Hi all, I tried post-layout simulation for a simple inverter, in the spectre.out file, it says: Notice from spectre during topology check. Only one connection to node 'vdd!' and output waveform confirmed that vdd is not actually supplied to internal transistors of the symbolized, extracted...
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