Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by mallikmarasu

  1. M

    start discussion on verification using system verilog

    Guyz , Why cant we start a thread regarding verification using system verilog instead of multiple threads so that it is easy for anyone to follow rythem. Here we can discuss all problems we are facing daily using sv and solutions for those. regards Mallik
  2. M

    how to compile sysetem verilog file using cadence tools

    hi , How to complie a systemeverilog file and how to simulate using system verilog programme using cadence tools
  3. M

    Suggestion regarding USB2 or USB3 projects

    Hi, Anybody working on usb2 or usb3 please post ur doubts or suggestions . Sothat it could useful for many people whose working on usb . regards Mallik
  4. M

    anybody have the test packet of usb2.0

    Hi All, I need some information regarding high speed usb . While the device in test mode, (if i set the device into transmit test packet ), what should be the test packet send by the device . Could any one give the pattern of tets packet .(53 bytes of data ). regards Mallik
  5. M

    Share your ideas on USB 3.0 architecture

    Re: USB 3.0 Share Ideas what exactly u r expecting ?
  6. M

    systemverilog interview questions post ur answers for these

    faq on system verilog Yaa man these are basic questions in systemverilog . If u know some of the questions u can post rite so that it can helpful for others .. i am trying to form a group of people whose working on systemverilog ..so that it can helpful for most of the people who started...
  7. M

    systemverilog interview questions post ur answers for these

    system verilog interview questions Qi1)What is callback ? (Qi2)What is factory pattern ? (Qi3)Explain the difference between data types logic and reg and wire . (Qi4)What is the need of clocking blocks ? (Qi5)What are the ways to avoid race condition between testbench and RTL using...
  8. M

    regarding modular inverse and modular reduction implementati

    Hi , Can u provide some documents for modular reduction and modular inverse regards mallik
  9. M

    abt modular exponetial ,inverse and multiplacation

    Hi how to implement the modular exponential ,modular inverse functions in verilog . or post some material regarding this. regards Mallik
  10. M

    regarding discussion abt verification

    hi , i am inviting u all to discuss abt verification. u can discuss here how to create verification environment, what stuff required to prove a good verification engineer,how to write bfms, etc. u can post material here or books upload/download section or paste links...
  11. M

    Looking for a book titled "Principles of Verifiable RTL Design"

    Re: Book needed hey, that book is there in book upload/download section. u go that section and search with the name "verilog" regards mallik 09739145146 Added after 25 seconds: hey, that book is there in book upload/download section. u go that section and search...
  12. M

    IRDA protocol specifications

    hi here i have attached irda protocol specification.
  13. M

    hi update (post ) ur projects here

    Hi all if u have any projects post here so that it can helpfull to others.
  14. M

    Developing HDL on a PIC card with FPGA

    Re: FPGA PCI development hi i need some good projects for exercise purpose regards mallik

Part and Inventory Search