Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by malisvce

  1. M

    clock network delay difference in primetime with OCV

    The delay difference in ocv mode was due to slew degradation. the tool degrades slew only in max paths and not in min paths. there is a variable to remove this from happening.....rc_degrade_min_slew_when_rd_less_than_rnet thanks artmalik for ur responses.
  2. M

    Cadence Encounter RTL compiler: Timing issues

    how about set_dont_touch or something like that
  3. M

    clock network delay difference in primetime with OCV

    Yes, the documents explains the aocv strategy. Do anyone have any info if this is enabled by default with operating conditions set to on chip variation? I am seeing different derating factor for capture clock network insertion delay based on clock path length etc, so it looks like aocv. But...
  4. M

    clock network delay difference in primetime with OCV

    @ artmalik: thanks for the response. I am uploading the netlist, WC library .db file and the max corner spef file. Is there any chance its coming from these, I dont think so, but checking just in case. or is the PT tool calculating it internally?
  5. M

    clock network delay difference in primetime with OCV

    Hello I tried doing primetime analysis with single wc library. The clock network delay I see in with operating condition set to single is 1.15 ns. However, for the same path, if I enable on chip variation, I am seeing a clock network delay of 1.01 ns. further in on chip variation mode, if I...
  6. M

    Should we declare test_se as a ideal_net so it will not be bufferred?

    Thanks for the responses. The harm is wasted resources. I am only wondering how to avoid them if its not needed. For example, if I set ideal net in DC, set_false path in ICC and continue, I am assuming ICC will not insert huge number of buffers for timing closure, but a limited number of...
  7. M

    Should we declare test_se as a ideal_net so it will not be bufferred?

    Hello All, I am using to DC to synthjesise a RTL and inserting scan as well I am currently declaring test_se as the default scan enable using set_dft_signal. Should I declare test_se as a ideal net during DC to avoid buffers on them or does DC not insert buffers on it automatically. Also...
See more

Part and Inventory Search

Back
Top